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yosys/passes
Akash Levy 8cdbd62394 opt_first_fit_alloc: address Greptile review
- pack_lanes: assert elem_w < 32 and pack the full element width instead
  of silently dropping bits >= 31.
- Remove the dead `cell` struct member and its unused assignment in run()
  (every emit helper shadows it with its own local `cell`).
- Decorrelate the pseudo-random bc bits from en (independent mix) so they
  no longer share an LFSR bit (e.g. en[7]/bc[0] for n=8).
- Add purpose comments to fingerprint_dsel and lane_of_bit.

Declined the std::stoi/std::stoll arg-parsing suggestion: it matches the
established convention in sibling passes (opt_argmax, opt_priority_onehot).

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-06-21 01:21:06 -07:00
..
cmds fix 2026-04-30 12:30:09 -07:00
equiv Bump to latest 2025-09-21 01:10:04 -07:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy Fixup NEW_ID usage 2026-05-27 00:09:12 -07:00
memory Fix cell naming issues 2026-02-13 01:05:51 -08:00
opt opt_first_fit_alloc: address Greptile review 2026-06-21 01:21:06 -07:00
pmgen More minor cleanup 2025-09-28 07:19:53 -07:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat fix: don't log error when getting non-top cells in -bb mode 2026-05-12 10:01:42 -07:00
silimate Small update 2026-06-18 05:26:28 -07:00
techmap necessary clock gate pass modifications 2026-06-01 17:19:23 -07:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00