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yosys/techlibs/anlogic
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Icenowy Zheng 634d7d1c14 Revert "Leave only real black box cells" 
This reverts commit 43030db5ff.

For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
..
anlogic_eqn.cc Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
arith_map.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
cells_map.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
cells_sim.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
eagle_bb.v Revert "Leave only real black box cells" 2018-12-17 23:20:40 +08:00
Makefile.inc Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
synth_anlogic.cc Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00