Johan Olby 63457de80e mul2dsp: normalize operand order ... Move the operand commute that puts the wider operand on A ahead of the min-width checks. Checking the min-widths first made an asymmetric rule (DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the wider operand on A; a product in the other order was rejected before the normalization.		2026-07-15 16:21:07 +02:00
..
choices	Merge pull request #4789 from YosysHQ/emil/sklansky-adder	2024-12-03 11:33:13 +01:00
abc9_map.v
abc9_model.v	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
abc9_unmap.v	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
adff2dff.v
CMakeLists.txt	Migrate build system to CMake	2026-06-03 08:58:10 +00:00
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v	techlibs: Add cmp2softlogic.v to common	2023-11-13 10:42:12 +01:00
dff2ff.v
gate2lut.v
gen_fine_ffs.py	simcells: Apply group tags	2024-10-15 07:35:40 +13:00
mul2dsp.v	mul2dsp: normalize operand order	2026-07-15 16:21:07 +02:00
opensta.cc	Migrate build system to CMake	2026-06-03 08:58:10 +00:00
opensta.h	opensta: refactor default command	2025-11-19 15:20:50 +01:00
pmux2mux.v
prep.cc	Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.	2026-01-23 01:14:35 +00:00
sdc_expand.cc	opensta, sdc_expand: mark as experimental	2025-11-19 15:31:17 +01:00
simcells.v	simcells: $dffsr and derivatives undefine S&R in logic tables	2026-03-19 19:27:30 +01:00
simlib.v	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
smtmap.v	Add smtmap.v describing the smt2 backend's behavior for undef bits	2022-10-20 15:48:18 +02:00
synth.cc	Add latch inference msg severity option.	2026-06-15 14:17:02 +02:00
techmap.v	simplemap: Moves $pmux mapping from techmap.v to simple map	2026-04-29 21:20:39 +00:00