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45 lines
854 B
Systemverilog
45 lines
854 B
Systemverilog
typedef enum {IDLE, RUN, STOP} state_t;
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typedef struct {
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logic [7:0] field1;
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int field2;
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} my_struct_t;
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// Submodule to handle the interface ports
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module submodule (
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my_ifc i_ifc,
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my_ifc o_ifc
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);
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// Connect the interface signals
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assign o_ifc.data = i_ifc.data;
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endmodule
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module test (
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input i_a,
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output o_a,
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input [0:0] i_b,
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output [0:0] o_b,
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input [3:0] i_c,
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output [3:0] o_c,
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input logic i_d,
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output logic o_d,
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input bit [7:0] i_e,
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output bit [7:0] o_e,
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input int i_f,
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output int o_f,
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input state_t i_h,
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output state_t o_h,
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input my_struct_t i_i,
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output my_struct_t o_i
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);
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assign o_a = i_a;
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assign o_b = i_b;
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assign o_c = i_c;
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assign o_d = i_d;
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assign o_e = i_e;
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assign o_f = i_f;
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assign o_h = i_h;
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assign o_i = i_i;
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endmodule
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