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65 lines
1.2 KiB
Text
65 lines
1.2 KiB
Text
# Test "casez to if/elif/else conversion" in backend
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read_verilog <<EOT
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module top(a, b, c, out);
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input wire a, b, c;
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output reg [3:0] out;
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always @(*) begin
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casez ({c, b, a})
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3'b??1: begin
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out = 0;
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end
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3'b?1?: begin
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out = 1;
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end
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3'b1??: begin
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out = 2;
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end
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default: begin
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out = 3;
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end
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endcase
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end
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endmodule
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EOT
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write_verilog roundtrip_proc_1.v
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design -stash gold
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read_verilog roundtrip_proc_1.v
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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prep
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miter -equiv -flatten -make_assert gold gate miter
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hierarchy -top miter
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sat -prove-asserts -verify
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design -reset
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read_verilog <<EOT
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module top(a, b, c, out);
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input wire a, b, c;
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output reg [3:0] out;
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always @(*) begin
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out <= 0;
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if (a) begin
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if (b)
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out <= 1;
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end else begin
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if (c)
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out <= 2;
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else
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out <= 3;
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end
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end
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endmodule
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EOT
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proc_clean
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write_verilog roundtrip_proc_2.v
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design -stash gold
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read_verilog roundtrip_proc_2.v
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design -stash gate
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design -copy-from gold -as gold top
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design -copy-from gate -as gate top
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prep
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miter -equiv -flatten -make_assert gold gate miter
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hierarchy -top miter
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sat -prove-asserts -verify
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