yosys/tests/verilog/genvar_loop_decl_3.ys at 61ef734c1d009e930f6fd52d4468b3392ae27768 - mirrors/yosys - Libre-Chip.org

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Zachary Snow b2e9717419 sv: support declaration in generate for initialization

This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.

2021-08-31 12:34:55 -06:00

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 read_verilog -sv genvar_loop_decl_3.sv
 proc
 equiv_make gold gate equiv
 equiv_simple
 equiv_status -assert