mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
11 lines
428 B
Plaintext
11 lines
428 B
Plaintext
read_verilog ../common/tribuf.v
|
|
hierarchy -top tristate
|
|
proc
|
|
flatten
|
|
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd tristate # Constrain all select calls below inside the top module
|
|
select -assert-count 3 t:TRELLIS_IO
|
|
select -assert-count 1 t:LUT4
|
|
select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D
|