| .. |
|
aiger
|
Run "clean -purge" on holes_module in its own design
|
2019-08-07 09:54:27 -07:00 |
|
blif
|
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
|
2019-08-06 04:47:55 +02:00 |
|
btor
|
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
|
2019-08-06 04:47:55 +02:00 |
|
edif
|
Add "whitebox" attribute, add "read_verilog -wb"
|
2019-04-18 17:45:47 +02:00 |
|
firrtl
|
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
|
2019-07-31 09:27:38 -07:00 |
|
ilang
|
Allow attributes on individual switch cases in RTLIL.
|
2019-07-08 11:34:58 +00:00 |
|
intersynth
|
Add "whitebox" attribute, add "read_verilog -wb"
|
2019-04-18 17:45:47 +02:00 |
|
json
|
Implement improved JSON attr/param encoding
|
2019-08-01 12:34:52 +02:00 |
|
protobuf
|
Support filename rewrite in backends
|
2019-06-18 14:39:52 -07:00 |
|
simplec
|
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
|
2019-08-06 04:47:55 +02:00 |
|
smt2
|
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
|
2019-08-06 04:47:55 +02:00 |
|
smv
|
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
|
2019-08-06 04:47:55 +02:00 |
|
spice
|
Add "whitebox" attribute, add "read_verilog -wb"
|
2019-04-18 17:45:47 +02:00 |
|
table
|
Add "whitebox" attribute, add "read_verilog -wb"
|
2019-04-18 17:45:47 +02:00 |
|
verilog
|
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
|
2019-08-06 04:47:55 +02:00 |
