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67 lines
2.6 KiB
C++
67 lines
2.6 KiB
C++
#ifndef PATCH_H
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#define PATCH_H
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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YOSYS_NAMESPACE_BEGIN
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// No virtual methods — subclasses cannot be dispatched through a Patch pointer.
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struct RTLIL::Patch : public CellAdderMixin<RTLIL::Patch>
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{
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private:
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void gc(Cell* old_cell, bool track = false, pool<std::string>* src_pool = nullptr);
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protected:
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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void add(RTLIL::Process *process);
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Cell* commit_cell(std::unique_ptr<Cell> cell);
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Wire* commit_wire(std::unique_ptr<Wire> wire);
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pool<Wire*> leaves = {};
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public:
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Module* mod;
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SigMap* map;
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pool<Cell*>* removed_cells = nullptr;
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vector<std::unique_ptr<Wire>> wires_ = {};
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vector<std::unique_ptr<Cell>> cells_ = {};
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void connect(const RTLIL::SigSig &conn);
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void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
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const std::vector<RTLIL::SigSig> &connections() const;
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void patch(Cell* old_cell, IdString old_port, SigSpec new_sig);
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void patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>> &port_replacements);
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// Variants for "merge old_cell into an existing keep_cell" (e.g.
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// opt_merge): the old_cell's src attribute is collected and combined
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// with merge_src_into's existing src, and the result is set on
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// merge_src_into. Any new cells in cells_ also receive the combined src.
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void patch(Cell* old_cell, IdString old_port, SigSpec new_sig, Cell* merge_src_into);
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void patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>> &port_replacements, Cell* merge_src_into);
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// Flush staged cells_ / wires_ into the module without doing any
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// connect_incremental or gc. Each committed cell's src attribute is
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// pulled from `src_source` (typically the cell that's being expanded /
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// unmapped into the staged helpers, so source-location tracking carries
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// through transparently). Pass nullptr for src_source if the staged
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// helpers have no natural ancestor.
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void commit_inheriting_src(Cell* src_source);
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RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
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RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
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RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
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RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
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RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
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RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src);
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Patch(Module* mod, SigMap* map = nullptr) : mod(mod), map(map) {}
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};
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YOSYS_NAMESPACE_END
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#endif
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