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yosys/frontends/verilog
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whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00
Makefile.inc Read bigger Verilog files. 2019-05-18 14:20:30 +03:00
preproc.cc Add check for valid macro names in macro definitions 2019-11-07 13:30:03 +01:00
verilog_frontend.cc Add "verilog_defines -list" and "verilog_defines -reset" 2019-10-21 13:35:56 +02:00
verilog_frontend.h Add specify parser 2019-04-23 21:36:59 +02:00
verilog_lexer.l sv: Correct parsing of always_comb, always_ff and always_latch 2019-11-21 20:27:19 +00:00
verilog_parser.y kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 2019-12-04 11:59:36 +00:00