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https://github.com/YosysHQ/yosys
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483 lines
No EOL
14 KiB
Verilog
483 lines
No EOL
14 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA,
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PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);
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parameter INIT = 0;
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parameter OPTION_SPLIT = 0;
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parameter PORT_A_WIDTH = 1;
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parameter PORT_A_WR_BE_WIDTH = 1;
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parameter PORT_B_WIDTH = 1;
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parameter PORT_B_WR_BE_WIDTH = 1;
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input PORT_A_CLK;
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input [14:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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input PORT_A_WR_EN;
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input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
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input PORT_A_CLK_EN;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_B_CLK;
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input [14:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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input PORT_B_WR_EN;
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input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
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input PORT_B_CLK_EN;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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// Fixed mode settings
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localparam [ 0:0] SYNC_FIFO1_i = 1'd0;
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localparam [ 0:0] FMODE1_i = 1'd0;
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localparam [ 0:0] POWERDN1_i = 1'd0;
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localparam [ 0:0] SLEEP1_i = 1'd0;
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localparam [ 0:0] PROTECT1_i = 1'd0;
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localparam [11:0] UPAE1_i = 12'd10;
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localparam [11:0] UPAF1_i = 12'd10;
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localparam [ 0:0] SYNC_FIFO2_i = 1'd0;
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localparam [ 0:0] FMODE2_i = 1'd0;
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localparam [ 0:0] POWERDN2_i = 1'd0;
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localparam [ 0:0] SLEEP2_i = 1'd0;
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localparam [ 0:0] PROTECT2_i = 1'd0;
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localparam [10:0] UPAE2_i = 11'd10;
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localparam [10:0] UPAF2_i = 11'd10;
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// Width mode function
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function [2:0] mode;
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input integer width;
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case (width)
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1: mode = 3'b101;
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2: mode = 3'b110;
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4: mode = 3'b100;
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8,9: mode = 3'b001;
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16, 18: mode = 3'b010;
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32, 36: mode = 3'b011;
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default: mode = 3'b000;
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endcase
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endfunction
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function [36863:0] pack_init;
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integer i;
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reg [35:0] ri;
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for (i = 0; i < (OPTION_SPLIT ? 512 : 1024); i = i + 1) begin
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ri = INIT[i*36 +: 36];
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pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18],
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ri[17], ri[8], ri[16:9], ri[7:0]};
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end
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if (OPTION_SPLIT)
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pack_init[36863:18432] = 18432'bx;
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endfunction
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wire REN_A1_i;
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wire REN_A2_i;
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wire REN_B1_i;
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wire REN_B2_i;
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wire WEN_A1_i;
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wire WEN_A2_i;
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wire WEN_B1_i;
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wire WEN_B2_i;
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wire [1:0] BE_A1_i;
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wire [1:0] BE_A2_i;
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wire [1:0] BE_B1_i;
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wire [1:0] BE_B2_i;
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wire [14:0] ADDR_A1_i;
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wire [13:0] ADDR_A2_i;
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wire [14:0] ADDR_B1_i;
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wire [13:0] ADDR_B2_i;
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wire [17:0] WDATA_A1_i;
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wire [17:0] WDATA_A2_i;
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wire [17:0] WDATA_B1_i;
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wire [17:0] WDATA_B2_i;
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wire [17:0] RDATA_A1_o;
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wire [17:0] RDATA_A2_o;
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wire [17:0] RDATA_B1_o;
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wire [17:0] RDATA_B2_o;
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// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
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localparam [ 2:0] RMODE_A1_i = mode(PORT_A_WIDTH);
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localparam [ 2:0] WMODE_A1_i = mode(PORT_A_WIDTH);
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localparam [ 2:0] RMODE_A2_i = mode(PORT_A_WIDTH);
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localparam [ 2:0] WMODE_A2_i = mode(PORT_A_WIDTH);
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localparam [ 2:0] RMODE_B1_i = mode(PORT_B_WIDTH);
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localparam [ 2:0] WMODE_B1_i = mode(PORT_B_WIDTH);
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localparam [ 2:0] RMODE_B2_i = mode(PORT_B_WIDTH);
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localparam [ 2:0] WMODE_B2_i = mode(PORT_B_WIDTH);
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assign REN_A1_i = PORT_A_CLK_EN;
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assign WEN_A1_i = PORT_A_CLK_EN & PORT_A_WR_EN;
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assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE;
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assign REN_B1_i = PORT_B_CLK_EN;
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assign WEN_B1_i = PORT_B_CLK_EN & PORT_B_WR_EN;
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assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE;
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case (PORT_A_WIDTH)
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9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA;
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18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA;
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36: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0], WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0]} = PORT_A_WR_DATA;
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default: assign WDATA_A1_i = PORT_A_WR_DATA; // 1,2,4
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endcase
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case (PORT_B_WIDTH)
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9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA;
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18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA;
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36: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0], WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0]} = PORT_B_WR_DATA;
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default: assign WDATA_B1_i = PORT_B_WR_DATA; // 1,2,4
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endcase
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case (PORT_A_WIDTH)
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9: assign PORT_A_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] };
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18: assign PORT_A_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] };
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36: assign PORT_A_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0], RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0]};
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default: assign PORT_A_RD_DATA = RDATA_A1_o; // 1,2,4
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endcase
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case (PORT_B_WIDTH)
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9: assign PORT_B_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] };
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18: assign PORT_B_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] };
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36: assign PORT_B_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0], RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0]};
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default: assign PORT_B_RD_DATA = RDATA_B1_o; // 1,2,4
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endcase
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defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0,
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UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
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UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
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};
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(* is_inferred = 1 *)
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(* is_split = 0 *)
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(* was_split_candidate = OPTION_SPLIT *)
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(* port_a_width = PORT_A_WIDTH *)
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(* port_b_width = PORT_B_WIDTH *)
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TDP36K #(
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.RAM_INIT(pack_init()),
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) _TECHMAP_REPLACE_ (
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.RESET_ni(1'b1),
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.CLK_A1_i(PORT_A_CLK),
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.ADDR_A1_i(PORT_A_ADDR),
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.WEN_A1_i(WEN_A1_i),
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.BE_A1_i(BE_A1_i),
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.WDATA_A1_i(WDATA_A1_i),
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.REN_A1_i(REN_A1_i),
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.RDATA_A1_o(RDATA_A1_o),
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.CLK_A2_i(PORT_A_CLK),
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.ADDR_A2_i(PORT_A_ADDR[13:0]),
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.WEN_A2_i(WEN_A1_i),
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.BE_A2_i(BE_A2_i),
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.WDATA_A2_i(WDATA_A2_i),
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.REN_A2_i(REN_A1_i),
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.RDATA_A2_o(RDATA_A2_o),
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.CLK_B1_i(PORT_B_CLK),
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.ADDR_B1_i(PORT_B_ADDR),
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.WEN_B1_i(WEN_B1_i),
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.BE_B1_i(BE_B1_i),
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.WDATA_B1_i(WDATA_B1_i),
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.REN_B1_i(REN_B1_i),
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.RDATA_B1_o(RDATA_B1_o),
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.CLK_B2_i(PORT_B_CLK),
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.ADDR_B2_i(PORT_B_ADDR[13:0]),
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.WEN_B2_i(WEN_B1_i),
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.BE_B2_i(BE_B2_i),
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.WDATA_B2_i(WDATA_B2_i),
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.REN_B2_i(REN_B1_i),
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.RDATA_B2_o(RDATA_B2_o),
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.FLUSH1_i(1'b0),
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.FLUSH2_i(1'b0)
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);
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endmodule
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module \$__QLF_TDP36K_MERGED (...);
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parameter INIT1 = 0;
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parameter PORT_A1_WIDTH = 1;
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parameter PORT_B1_WIDTH = 1;
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parameter PORT_A1_WR_BE_WIDTH = 1;
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parameter PORT_B1_WR_BE_WIDTH = 1;
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input PORT_A1_CLK;
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input [14:0] PORT_A1_ADDR;
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input [PORT_A1_WIDTH-1:0] PORT_A1_WR_DATA;
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input PORT_A1_WR_EN;
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input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE;
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input PORT_A1_CLK_EN;
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output [PORT_A1_WIDTH-1:0] PORT_A1_RD_DATA;
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input PORT_B1_CLK;
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input [14:0] PORT_B1_ADDR;
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input [PORT_B1_WIDTH-1:0] PORT_B1_WR_DATA;
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input PORT_B1_WR_EN;
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input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE;
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input PORT_B1_CLK_EN;
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output [PORT_B1_WIDTH-1:0] PORT_B1_RD_DATA;
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parameter INIT2 = 0;
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parameter PORT_A2_WIDTH = 1;
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parameter PORT_B2_WIDTH = 1;
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parameter PORT_A2_WR_BE_WIDTH = 1;
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parameter PORT_B2_WR_BE_WIDTH = 1;
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input PORT_A2_CLK;
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input [14:0] PORT_A2_ADDR;
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input [PORT_A2_WIDTH-1:0] PORT_A2_WR_DATA;
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input PORT_A2_WR_EN;
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input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE;
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input PORT_A2_CLK_EN;
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output [PORT_A2_WIDTH-1:0] PORT_A2_RD_DATA;
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input PORT_B2_CLK;
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input [14:0] PORT_B2_ADDR;
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input [PORT_B2_WIDTH-1:0] PORT_B2_WR_DATA;
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input PORT_B2_WR_EN;
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input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE;
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input PORT_B2_CLK_EN;
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output [PORT_B2_WIDTH-1:0] PORT_B2_RD_DATA;
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// Fixed mode settings
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localparam [ 0:0] SYNC_FIFO1_i = 1'd0;
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localparam [ 0:0] FMODE1_i = 1'd0;
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localparam [ 0:0] POWERDN1_i = 1'd0;
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localparam [ 0:0] SLEEP1_i = 1'd0;
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localparam [ 0:0] PROTECT1_i = 1'd0;
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localparam [11:0] UPAE1_i = 12'd10;
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localparam [11:0] UPAF1_i = 12'd10;
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localparam [ 0:0] SYNC_FIFO2_i = 1'd0;
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localparam [ 0:0] FMODE2_i = 1'd0;
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localparam [ 0:0] POWERDN2_i = 1'd0;
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localparam [ 0:0] SLEEP2_i = 1'd0;
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localparam [ 0:0] PROTECT2_i = 1'd0;
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localparam [10:0] UPAE2_i = 11'd10;
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localparam [10:0] UPAF2_i = 11'd10;
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// Width mode function
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function [2:0] mode;
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input integer width;
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case (width)
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1: mode = 3'b101;
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2: mode = 3'b110;
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4: mode = 3'b100;
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8,9: mode = 3'b001;
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16, 18: mode = 3'b010;
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default: mode = 3'b000;
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endcase
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endfunction
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function [36863:0] pack_init;
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integer i;
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reg [35:0] ri;
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for (i = 0; i < 1024; i = i + 1) begin
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ri = {INIT2[i*18 +: 18], INIT1[i*18 +: 18]};
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pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], ri[17], ri[8], ri[16:9], ri[7:0]};
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end
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endfunction
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wire REN_A1_i;
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wire REN_A2_i;
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wire REN_B1_i;
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wire REN_B2_i;
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wire WEN_A1_i;
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wire WEN_A2_i;
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wire WEN_B1_i;
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wire WEN_B2_i;
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wire [1:0] BE_A1_i;
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wire [1:0] BE_A2_i;
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wire [1:0] BE_B1_i;
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wire [1:0] BE_B2_i;
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wire [14:0] ADDR_A1_i;
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wire [13:0] ADDR_A2_i;
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wire [14:0] ADDR_B1_i;
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wire [13:0] ADDR_B2_i;
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wire [17:0] WDATA_A1_i;
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wire [17:0] WDATA_A2_i;
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wire [17:0] WDATA_B1_i;
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wire [17:0] WDATA_B2_i;
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wire [17:0] RDATA_A1_o;
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wire [17:0] RDATA_A2_o;
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wire [17:0] RDATA_B1_o;
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wire [17:0] RDATA_B2_o;
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// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.)
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localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_WIDTH);
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localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_WIDTH);
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localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_WIDTH);
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localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_WIDTH);
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localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_WIDTH);
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localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_WIDTH);
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localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_WIDTH);
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localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_WIDTH);
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assign REN_A1_i = PORT_A1_CLK_EN;
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assign WEN_A1_i = PORT_A1_CLK_EN & PORT_A1_WR_EN;
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assign BE_A1_i = PORT_A1_WR_BE;
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assign REN_B1_i = PORT_B1_CLK_EN;
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assign WEN_B1_i = PORT_B1_CLK_EN & PORT_B1_WR_EN;
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assign BE_B1_i = PORT_B1_WR_BE;
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assign REN_A2_i = PORT_A2_CLK_EN;
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assign WEN_A2_i = PORT_A2_CLK_EN & PORT_A2_WR_EN;
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assign BE_A2_i = PORT_A2_WR_BE;
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assign REN_B2_i = PORT_B2_CLK_EN;
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assign WEN_B2_i = PORT_B2_CLK_EN & PORT_B2_WR_EN;
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assign BE_B2_i = PORT_B2_WR_BE;
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assign ADDR_A1_i = PORT_A1_ADDR;
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assign ADDR_B1_i = PORT_B1_ADDR;
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assign ADDR_A2_i = PORT_A2_ADDR;
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assign ADDR_B2_i = PORT_B2_ADDR;
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case (PORT_A1_WIDTH)
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9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA;
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18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA;
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default: assign WDATA_A1_i = PORT_A1_WR_DATA; // 1,2,4,8,16
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endcase
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|
|
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case (PORT_B1_WIDTH)
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9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA;
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18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA;
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default: assign WDATA_B1_i = PORT_B1_WR_DATA; // 1,2,4,8,16
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endcase
|
|
|
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case (PORT_A1_WIDTH)
|
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9: assign PORT_A1_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] };
|
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18: assign PORT_A1_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] };
|
|
default: assign PORT_A1_RD_DATA = RDATA_A1_o; // 1,2,4,8,16
|
|
endcase
|
|
|
|
case (PORT_B1_WIDTH)
|
|
9: assign PORT_B1_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] };
|
|
18: assign PORT_B1_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] };
|
|
default: assign PORT_B1_RD_DATA = RDATA_B1_o; // 1,2,4,8,16
|
|
endcase
|
|
|
|
case (PORT_A2_WIDTH)
|
|
9: assign { WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA;
|
|
18: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA;
|
|
default: assign WDATA_A2_i = PORT_A2_WR_DATA; // 1,2,4,8,16
|
|
endcase
|
|
|
|
case (PORT_B2_WIDTH)
|
|
9: assign { WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA;
|
|
18: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA;
|
|
default: assign WDATA_B2_i = PORT_B2_WR_DATA; // 1,2,4,8,16
|
|
endcase
|
|
|
|
case (PORT_A2_WIDTH)
|
|
9: assign PORT_A2_RD_DATA = { RDATA_A2_o[16], RDATA_A2_o[7:0] };
|
|
18: assign PORT_A2_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0] };
|
|
default: assign PORT_A2_RD_DATA = RDATA_A2_o; // 1,2,4,8,16
|
|
endcase
|
|
|
|
case (PORT_B2_WIDTH)
|
|
9: assign PORT_B2_RD_DATA = { RDATA_B2_o[16], RDATA_B2_o[7:0] };
|
|
18: assign PORT_B2_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0] };
|
|
default: assign PORT_B2_RD_DATA = RDATA_B2_o; // 1,2,4,8,16
|
|
endcase
|
|
|
|
defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1,
|
|
UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i,
|
|
UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i
|
|
};
|
|
|
|
(* is_inferred = 1 *)
|
|
(* is_split = 1 *)
|
|
(* port_a1_width = PORT_A1_WIDTH *)
|
|
(* port_a2_width = PORT_A2_WIDTH *)
|
|
(* port_b1_width = PORT_B1_WIDTH *)
|
|
(* port_b2_width = PORT_B2_WIDTH *)
|
|
TDP36K #(
|
|
.RAM_INIT(pack_init()),
|
|
) _TECHMAP_REPLACE_ (
|
|
.RESET_ni(1'b1),
|
|
.WDATA_A1_i(WDATA_A1_i),
|
|
.WDATA_A2_i(WDATA_A2_i),
|
|
.RDATA_A1_o(RDATA_A1_o),
|
|
.RDATA_A2_o(RDATA_A2_o),
|
|
.ADDR_A1_i(ADDR_A1_i),
|
|
.ADDR_A2_i(ADDR_A2_i),
|
|
.CLK_A1_i(PORT_A1_CLK),
|
|
.CLK_A2_i(PORT_A2_CLK),
|
|
.REN_A1_i(REN_A1_i),
|
|
.REN_A2_i(REN_A2_i),
|
|
.WEN_A1_i(WEN_A1_i),
|
|
.WEN_A2_i(WEN_A2_i),
|
|
.BE_A1_i(BE_A1_i),
|
|
.BE_A2_i(BE_A2_i),
|
|
|
|
.WDATA_B1_i(WDATA_B1_i),
|
|
.WDATA_B2_i(WDATA_B2_i),
|
|
.RDATA_B1_o(RDATA_B1_o),
|
|
.RDATA_B2_o(RDATA_B2_o),
|
|
.ADDR_B1_i(ADDR_B1_i),
|
|
.ADDR_B2_i(ADDR_B2_i),
|
|
.CLK_B1_i(PORT_B1_CLK),
|
|
.CLK_B2_i(PORT_B2_CLK),
|
|
.REN_B1_i(REN_B1_i),
|
|
.REN_B2_i(REN_B2_i),
|
|
.WEN_B1_i(WEN_B1_i),
|
|
.WEN_B2_i(WEN_B2_i),
|
|
.BE_B1_i(BE_B1_i),
|
|
.BE_B2_i(BE_B2_i),
|
|
|
|
.FLUSH1_i(1'b0),
|
|
.FLUSH2_i(1'b0)
|
|
);
|
|
|
|
endmodule |