Eddie Hung 15188033da Add variable length support to xilinx_srl		2019-08-21 17:34:40 -07:00
..
tests
.gitignore
abc_xc7.box	Fix $__XILINX_MUXF78 box timing	2019-07-01 14:04:06 -07:00
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
cells_map.v	xilinx: Fix missing cell name underscore in cells_map.v	2019-07-25 08:19:07 +01:00
cells_sim.v	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
cells_xtra.sh
cells_xtra.v
ff_map.v	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
lut_map.v
lutrams.txt	Work in progress for renaming labels/options in synth_xilinx	2019-07-18 14:20:43 -07:00
lutrams_map.v	Work in progress for renaming labels/options in synth_xilinx	2019-07-18 14:20:43 -07:00
Makefile.inc	Update Makefile too	2019-07-18 14:51:55 -07:00
mux_map.v
synth_xilinx.cc	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
xc6s_brams.txt	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc6s_brams_bb.v	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc6s_brams_map.v	RST -> RSTBRST for RAMB8BWER	2019-07-29 16:05:44 -07:00
xc7_brams.txt	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc7_brams_bb.v	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
xc7_brams_map.v	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00