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15 lines
267 B
Text
15 lines
267 B
Text
# Multiple names for an output port
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logger -expect error "Missing details for module port" 1
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read_verilog << EOF
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module gate_multi_output (
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a,
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.c(b),
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.b(b)
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);
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input a;
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output b;
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assign b = a;
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endmodule
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EOF
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logger -check-expected
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design -reset
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