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22 lines
317 B
Text
22 lines
317 B
Text
# Equivalence
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read_verilog << EOF
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module gold(input a, input b, output c);
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assign c = a + b;
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endmodule
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module gate_header (
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.a(x),
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.b(y),
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.c(z)
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);
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input x;
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input y;
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output z;
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assign z = x + y;
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endmodule
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EOF
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equiv_make gold gate_header equiv_header
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equiv_simple
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equiv_status -assert
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