mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-25 19:36:21 +00:00
87 lines
1,010 B
CMake
87 lines
1,010 B
CMake
if (YOSYS_ENABLE_ABC)
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set(abc_requires abc abc9)
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endif()
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yosys_pass(synth
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synth.cc
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DEFINITIONS
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$<$<BOOL:${YOSYS_ENABLE_ABC}>:YOSYS_ENABLE_ABC>
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REQUIRES
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${abc_requires}
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alumacc
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arith_tree
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booth
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check
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clean
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flatten
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flowmap
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fsm
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hierarchy
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memory
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memory_map
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opt
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opt_clean
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opt_expr
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peepopt
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proc
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share
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stat
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techmap
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wreduce
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DATA_FILES
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simlib.v
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simcells.v
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techmap.v
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smtmap.v
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pmux2mux.v
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adff2dff.v
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dff2ff.v
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gate2lut.v
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cmp2lut.v
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mul2dsp.v
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abc9_model.v
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abc9_map.v
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abc9_unmap.v
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cmp2lcu.v
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cmp2softlogic.v
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choices/kogge-stone.v
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choices/han-carlson.v
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choices/sklansky.v
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)
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yosys_pass(prep
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prep.cc
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REQUIRES
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check
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flatten
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future
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hierarchy
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memory_collect
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memory_dff
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memory_memx
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opt
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opt_clean
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opt_expr
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proc
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sort
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stat
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wreduce
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)
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yosys_pass(opensta
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opensta.cc
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)
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yosys_pass(sdc_expand
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sdc_expand.cc
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REQUIRES
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chtype
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design
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hierarchy
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icell_liberty
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memory
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opensta
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proc
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read_verilog
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write_verilog
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)
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