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https://github.com/YosysHQ/yosys
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28 lines
337 B
CMake
28 lines
337 B
CMake
yosys_pass(synth_achronix
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synth_achronix.cc
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REQUIRES
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abc
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blackbox
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check
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clean
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deminout
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dfflegalize
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flatten
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hierarchy
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iopadmap
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memory_map
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opt
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proc
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read_verilog
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setundef
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stat
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synth
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techmap
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tribuf
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write_verilog
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DATA_DIR
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achronix
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DATA_FILES
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speedster22i/cells_sim.v
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speedster22i/cells_map.v
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)
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