mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-31 16:33:19 +00:00
c2b7ad3b28
Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> |
||
|---|---|---|
| .. | ||
| .gitignore | ||
| add_sub.ys | ||
| blockram.ys | ||
| counter.ys | ||
| dffs.ys | ||
| fsm.ys | ||
| latches.ys | ||
| logic.ys | ||
| lutram.ys | ||
| mux.ys | ||
| run-test.sh | ||
| shifter.ys | ||
| tribuf.ys | ||