This website requires JavaScript.
Explore
Help
Register
Sign in
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2025-08-11 21:50:54 +00:00
Code
Activity
600079e281
yosys
/
techlibs
/
xilinx
History
Download ZIP
Download TAR.GZ
Marcelina Kościelnicka
be9595e18f
xilinx: Add RAMB4* blackboxes
2022-03-21 13:11:52 +01:00
..
tests
.gitignore
abc9_model.v
arith_map.v
brams_init.py
cells_map.v
cells_sim.v
cells_xtra.py
cells_xtra.v
ff_map.v
lut4_lutrams.txt
lut6_lutrams.txt
lut_map.v
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc
xc2v_brams.txt
xc2v_brams_map.v
xc3s_mult_map.v
xc3sa_brams.txt
xc3sda_brams.txt
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc