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Code Activity
yosys/tests/arch
History
Eddie Hung 5f97086302 Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-02 15:14:12 -08:00
..
anlogic Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
common Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 2019-12-16 21:48:21 -08:00
ecp5 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
efinix Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
gowin Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
ice40 Revert insertion of 'reg', leave note behind 2020-01-01 09:05:46 -08:00
xilinx Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-02 15:14:12 -08:00
run-test.sh Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00