mirror of
https://github.com/YosysHQ/yosys
synced 2026-08-06 22:34:16 +00:00
3006280d70
run_fixed inferred a fixed length shift register from a chain of FDRE flops but assigned it ENPOL 2, which the cells_map template reads as no enable and ties the enable high. FDRE has an active high clock enable, so the shift register shifted every cycle and ignored stalls. Give FDRE and FDRE_1 chains ENPOL 1 so the active high enable is kept. Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path. |
||
|---|---|---|
| .. | ||
| analogdevices | ||
| anlogic | ||
| common | ||
| ecp5 | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| ice40 | ||
| intel_alm | ||
| machxo2 | ||
| microchip | ||
| nanoxplore | ||
| nexus | ||
| quicklogic | ||
| xilinx | ||
| generate_mk.py | ||