Eddie Hung 7939727d14 Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts ... Unpermute LUT ordering for ice40/ecp5/xilinx		2020-01-28 11:55:51 -08:00
..
cmds	redirect fuser stderr to /dev/null	2020-01-28 10:02:41 +01:00
equiv
fsm	fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.	2020-01-14 22:49:20 +01:00
hierarchy
memory
opt
pmgen	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards	2020-01-27 14:02:13 -08:00
proc
sat	Merge pull request #1567 from YosysHQ/eddie/sat_init_warning	2020-01-28 17:40:28 +01:00
techmap	Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate	2020-01-28 17:24:54 +01:00
tests