Eddie Hung ad602438b8 Add retime test		2019-04-05 16:28:46 -07:00
..
aiger	Support and differentiate between ASCII and binary AIG testing	2019-02-08 12:41:59 -08:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm
hana
liberty	Liberty file parser now accepts superfluous ;	2019-03-27 15:16:19 +01:00
lut	cmp2lut: new techmap pass.	2019-01-02 07:53:31 +00:00
memories
opt	Fix WREDUCE on FF not fixing ARST_VALUE parameter.	2019-02-22 10:30:42 -08:00
realmath
sat	Allow $size and $bits in verilog mode, actually check test case	2017-09-29 11:56:43 +02:00
share
simple	Add retime test	2019-04-05 16:28:46 -07:00
smv
sva	Fix "verific -extnets" for more complex situations	2019-03-26 14:17:46 +01:00
svinterfaces	Add missing .gitignore	2018-12-06 07:29:37 +01:00
techmap
tools	Merge https://github.com/YosysHQ/yosys into read_aiger	2019-03-19 08:52:31 -07:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	Address requested changes - don't require non-$ name.	2019-02-22 16:06:10 -08:00
vloghtb