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https://github.com/YosysHQ/yosys
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125 lines
2.8 KiB
Systemverilog
125 lines
2.8 KiB
Systemverilog
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module TopModule(
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input logic clk,
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input logic rst,
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output logic [21:0] outOther,
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input logic [1:0] sig,
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input logic flip,
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output logic [1:0] sig_out,
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MyInterface.submodule1 interfaceInstanceAtTop,
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output logic [15:0] passThrough);
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MyInterface #(.WIDTH(4)) MyInterfaceInstance();
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SubModule1 u_SubModule1 (
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.clk(clk),
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.rst(rst),
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.u_MyInterface(MyInterfaceInstance),
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.u_MyInterfaceFromTop(interfaceInstanceAtTop),
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.outOther(outOther),
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.sig (sig)
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);
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assign sig_out = MyInterfaceInstance.mysig_out;
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assign MyInterfaceInstance.setting = flip;
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assign passThrough = MyInterfaceInstance.passThrough;
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endmodule
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interface MyInterface #(
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parameter WIDTH = 3)(
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);
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logic setting;
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logic [WIDTH-1:0] other_setting;
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logic [1:0] mysig_out;
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logic [15:0] passThrough;
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modport submodule1 (
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input setting,
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output other_setting,
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output mysig_out,
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output passThrough
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);
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modport submodule2 (
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input setting,
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output other_setting,
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input mysig_out,
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output passThrough
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);
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endinterface
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module SubModule1(
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input logic clk,
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input logic rst,
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MyInterface.submodule1 u_MyInterface,
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MyInterface.submodule1 u_MyInterfaceFromTop,
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input logic [1:0] sig,
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output logic [21:0] outOther
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);
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always_ff @(posedge clk or posedge rst)
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if(rst)
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u_MyInterface.mysig_out <= 0;
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else begin
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if(u_MyInterface.setting)
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u_MyInterface.mysig_out <= sig;
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else
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u_MyInterface.mysig_out <= ~sig;
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end
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MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
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SubModule2 u_SubModule2 (
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.clk(clk),
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.rst(rst),
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.u_MyInterfaceFromTopDown(u_MyInterfaceFromTop),
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.u_MyInterfaceInSub2(u_MyInterface),
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.u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
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);
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assign outOther = MyInterfaceInstanceInSub.other_setting;
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assign MyInterfaceInstanceInSub.setting = 0;
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assign MyInterfaceInstanceInSub.mysig_out = sig;
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endmodule
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module SubModule2(
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input logic clk,
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input logic rst,
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MyInterface.submodule2 u_MyInterfaceInSub2,
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MyInterface.submodule1 u_MyInterfaceFromTopDown,
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MyInterface.submodule2 u_MyInterfaceInSub3
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);
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assign u_MyInterfaceFromTopDown.mysig_out = u_MyInterfaceFromTop.setting ? 10 : 20;
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always_comb begin
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if (u_MyInterfaceInSub3.mysig_out == 2'b00)
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u_MyInterfaceInSub3.other_setting[21:0] = 1000;
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else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
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u_MyInterfaceInSub3.other_setting[21:0] = 2000;
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else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
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u_MyInterfaceInSub3.other_setting[21:0] = 3000;
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else
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u_MyInterfaceInSub3.other_setting[21:0] = 4000;
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end
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assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
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assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
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endmodule
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