This website requires JavaScript.
Explore
Help
Register
Sign in
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2026-07-15 11:45:41 +00:00
Code
Activity
5efc95f7d9
yosys
/
frontends
History
Akash Levy
652a9a63b2
Update to latest and fix all disabled tests
2025-09-28 01:33:08 -07:00
..
aiger
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
aiger2
Remove .c_str() calls from log()/log_error()
2025-09-11 20:59:37 +00:00
ast
verilog: Bufnorm cell backend and frontend support
2025-09-17 14:01:09 +02:00
blif
Bump to latest
2025-09-21 01:10:04 -07:00
json
Use fast path for 32-bit Const integer constructor in more places
2025-09-16 03:17:24 +00:00
liberty
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
rpc
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
rtlil
Use fast path for 32-bit Const integer constructor in more places
2025-09-16 03:17:24 +00:00
verific
Bump to latest
2025-09-21 01:10:04 -07:00
verilog
Merge pull request
#5315
from YosysHQ/emil/write_rtlil-no-sort
2025-09-22 11:14:39 +02:00