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74 lines
1.4 KiB
Systemverilog
74 lines
1.4 KiB
Systemverilog
module sub_mod(input i_in, output o_out);
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assign o_out = i_in;
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endmodule
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module test(i_clk, i, i_reg, o_reg, o_wire, o_mr, o_mw, o_ml);
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input i_clk;
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input i;
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input i_reg;
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output o_reg;
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output o_wire;
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output o_mr, o_mw, o_ml;
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// Enable this to see how it doesn't fail on yosys although it should
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//reg o_wire;
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// Enable this instead of the above to see how logic can be mapped to a wire
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logic o_wire;
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// Enable this to see how it doesn't fail on yosys although it should
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//reg i_reg;
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// Disable this to see how it doesn't fail on yosys although it should
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//reg o_reg;
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logic l_reg;
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// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
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assign l_reg = !o_reg;
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initial o_reg = 1'b0;
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always @(posedge i_clk)
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begin
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o_reg <= !o_reg;
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l_reg <= !o_reg;
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end
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assign o_wire = !o_reg;
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// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
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assign l_reg = !o_reg;
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sub_mod sm_inst (
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.i_in(1'b1),
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.o_out(o_reg)
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);
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wire mw1[0:1];
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wire mw2[0:1];
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wire mw3[0:1];
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reg mr1[0:1];
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reg mr2[0:1];
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reg mr3[0:1];
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logic ml1[0:1];
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logic ml2[0:1];
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logic ml3[0:1];
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assign o_mw = mw1[i];
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assign o_mr = mr1[i];
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assign o_ml = ml1[i];
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assign mw1[1] = 1'b1;
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//assign mr1[1] = 1'b1;
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assign ml1[1] = 1'b1;
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always @(posedge i_clk)
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begin
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mr2[0] = 1'b0;
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mw2[0] = 1'b0;
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ml2[0] = 1'b0;
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end
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always @(posedge i_clk)
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begin
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mr3[0] <= 1'b0;
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mw3[0] <= 1'b0;
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ml3[0] <= 1'b0;
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end
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endmodule
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