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yosys/techlibs/intel
Ben Widawsky 05d8cc4567 Fix formatting for synth_intel.cc
This is realized through the recently added .clang-format file.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-09 08:40:05 -07:00
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a10gx
common
cyclone10
cycloneiv
cycloneive Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
cyclonev Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
max10
Makefile.inc
synth_intel.cc Fix formatting for synth_intel.cc 2019-05-09 08:40:05 -07:00