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yosys/techlibs/xilinx/example_zed_counter
History
James Walmsley 40b3551b45 [EXAMPLES] Ported the mojo counter example to Zynq ZED board. 
Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
2013-10-27 21:48:39 +01:00
..
example.sh [EXAMPLES] Ported the mojo counter example to Zynq ZED board. 2013-10-27 21:48:39 +01:00
example.ucf [EXAMPLES] Ported the mojo counter example to Zynq ZED board. 2013-10-27 21:48:39 +01:00
example.v [EXAMPLES] Ported the mojo counter example to Zynq ZED board. 2013-10-27 21:48:39 +01:00
README [EXAMPLES] Ported the mojo counter example to Zynq ZED board. 2013-10-27 21:48:39 +01:00

README 

This is a simple example for Yosys synthesis targeting the ZED FPGA
development board [1, 2]. Simple script for xst-based synthesis (incl.
generation of reference edif files) and uploading to the board can be
found here [3].

[1] http://www.zedboard.org/
[2] https://www.xilinx.com/zynq/
[3] http://verilog.james.walms.co.uk/