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60 lines
1.7 KiB
Verilog
60 lines
1.7 KiB
Verilog
module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s == 0) o <= i[0*W+:W];
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else if (s == 1) o <= i[1*W+:W];
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else if (s == 2) o <= i[2*W+:W];
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else if (s == 3) o <= i[3*W+:W];
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else o <= {W{1'bx}};
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endmodule
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module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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if (s == 0) o <= i[0*W+:W];
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if (s == 1) o <= i[1*W+:W];
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if (s == 2) o <= i[2*W+:W];
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if (s == 3) o <= i[3*W+:W];
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if (s == 4) o <= i[4*W+:W];
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end
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endmodule
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module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s != 0)
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if (s != 1)
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if (s != 2)
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if (s != 3)
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if (s != 4) o <= i[4*W+:W];
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else o <= i[0*W+:W];
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else o <= i[3*W+:W];
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else o <= i[2*W+:W];
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else o <= i[1*W+:W];
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else o <= {W{1'bx}};
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endmodule
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module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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if (s == 0) o <= i[0*W+:W];
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if (s == 1) o <= i[1*W+:W];
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if (s == 2) o[W-2:0] <= i[2*W+:W-1];
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if (s == 3) o <= i[3*W+:W];
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if (s == 4) o <= i[4*W+:W];
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end
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endmodule
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module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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if (s == 0) o <= i[0*W+:W];
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// else if (s == 1) o <= i[1*W+:W];
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// else if (s == 2) o <= i[2*W+:W];
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else if (s == 3) o <= i[3*W+:W];
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else o <= {W{1'bx}};
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end
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endmodule
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