mirror of
https://github.com/YosysHQ/yosys
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109 lines
3.4 KiB
C++
109 lines
3.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/threading.h"
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#include "kernel/celltypes.h"
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#include "kernel/yosys_common.h"
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#include "passes/opt/opt_clean/keep_cache.h"
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#ifndef OPT_CLEAN_SHARED_H
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#define OPT_CLEAN_SHARED_H
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YOSYS_NAMESPACE_BEGIN
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struct AnalysisContext {
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SigMap assign_map;
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const RTLIL::Module *mod;
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ParallelDispatchThreadPool::Subpool &subpool;
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AnalysisContext(RTLIL::Module* m, ParallelDispatchThreadPool::Subpool &p) : assign_map(m), mod(m), subpool(p) {}
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};
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struct RmStats {
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int count_rm_cells = 0;
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int count_rm_wires = 0;
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void log()
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{
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if (count_rm_cells > 0 || count_rm_wires > 0)
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YOSYS_NAMESPACE_PREFIX log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
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}
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};
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struct Flags {
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bool purge = false;
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bool verbose = false;
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};
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struct CleanRunContext {
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CellTypes ct_reg;
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CellTypes ct_all;
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RmStats stats;
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ParallelDispatchThreadPool thread_pool;
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std::vector<RTLIL::Module*> selected_modules;
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keep_cache_t keep_cache;
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Flags flags;
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private:
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// Helper to compute thread pool size
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static int compute_thread_pool_size(RTLIL::Design* design) {
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int thread_pool_size = 0;
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for (auto module : design->selected_unboxed_whole_modules())
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if (!module->has_processes())
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thread_pool_size = std::max(thread_pool_size,
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ThreadPool::work_pool_size(0, module->cells_size(), 1000));
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return thread_pool_size;
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}
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static std::vector<RTLIL::Module*> get_selected_modules(RTLIL::Design* design) {
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std::vector<RTLIL::Module*> modules;
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for (auto module : design->selected_unboxed_whole_modules())
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if (!module->has_processes())
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modules.push_back(module);
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return modules;
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}
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public:
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CleanRunContext(RTLIL::Design* design, Flags f)
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: thread_pool(compute_thread_pool_size(design)),
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selected_modules(get_selected_modules(design)),
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keep_cache(f.purge, thread_pool, selected_modules),
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flags(f)
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{
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ct_reg.setup_internals_mem();
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ct_reg.setup_internals_anyinit();
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ct_reg.setup_stdcells_mem();
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ct_all.setup(design);
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}
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~CleanRunContext() {
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ct_reg.clear();
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ct_all.clear();
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}
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};
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void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose);
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void rmunused_module_cells(Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx);
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bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, CleanRunContext &clean_ctx);
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bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose);
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YOSYS_NAMESPACE_END
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#endif /* OPT_CLEAN_SHARED_H */
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