mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
2e37e62e6b
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
18 lines
772 B
Text
18 lines
772 B
Text
read_verilog ../common/fsm.v
|
|
hierarchy -top fsm
|
|
proc
|
|
flatten
|
|
|
|
equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev
|
|
async2sync
|
|
miter -equiv -make_assert -flatten gold gate miter
|
|
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd fsm # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 6 t:MISTRAL_FF
|
|
select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
|
|
select -assert-count 5 t:MISTRAL_ALUT5
|
|
select -assert-count 1 t:MISTRAL_ALUT6
|
|
select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
|