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https://github.com/YosysHQ/yosys
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fc28bf55aa
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify appear to interpret attribute values insensitive
to case. There is currently no way to do this in Yosys (attrmap
can only change case of attribute names).
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
`default_nettype none
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module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire write_enable, clk,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sp
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`default_nettype none
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module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk, write_enable,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in_w] <= data_in;
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data_out_r <= memory[address_in_r];
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end
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp
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