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11 lines
180 B
Text
11 lines
180 B
Text
read_verilog <<EOF
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module top(a, b, s, y);
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input wire [7:0] a;
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input wire [7:0] b;
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input wire s;
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output wire y;
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assign y = s ? |a : |b;
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endmodule
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EOF
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share -force
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