Philippe Sauter 5c77c73888 extract: trim port widths to minimum ... This does not yet seem to work completely as intended. The idea is to trim the port widths of the extracted circuits, so that it does not leave X bits as padding at the MSBs.		2024-06-14 10:03:17 +02:00
..
cmds	rename -witness: Bug fix and rename formal cells	2024-03-04 16:53:03 +01:00
equiv	equiv_simple: Take FFs into account for driver map	2024-02-21 12:05:52 +01:00
fsm	add option to fsm_detect to ignore self-resetting	2023-01-30 16:12:53 +01:00
hierarchy	hierarchy: Without a known top module, derive all deferred modules	2024-02-06 10:31:40 +01:00
memory	opt_mem, memory_*: Refuse to operate in presence of processes	2024-02-23 12:27:53 +01:00
opt	opt_mem, memory_*: Refuse to operate in presence of processes	2024-02-23 12:27:53 +01:00
pmgen	Address SigBit/SigSpec confusion issues under c++20	2024-02-08 17:48:36 +01:00
proc	Merge pull request #4218 from kivikakk/proc_rom-actionless-switch	2024-02-19 16:21:40 +01:00
sat	Merge pull request #3972 from nakengelhardt/celledges_shift_ops	2024-03-08 09:35:47 +01:00
techmap	extract: trim port widths to minimum	2024-06-14 10:03:17 +02:00
tests	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00