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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
61 lines
2.2 KiB
C++
61 lines
2.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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#include <string.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct FsmInfoPass : public Pass {
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FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_info [selection]\n");
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log("\n");
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log("This pass dumps all internal information on FSM cells. It can be useful for\n");
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log("analyzing the synthesis process and is called automatically by the 'fsm'\n");
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log("pass so that this information is included in the synthesis log file.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
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extra_args(args, 1, design);
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for (auto mod : design->selected_modules())
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for (auto cell : mod->selected_cells())
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if (cell->type == ID($fsm)) {
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log("\n");
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log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod));
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FsmData fsm_data;
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fsm_data.copy_from_cell(cell);
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fsm_data.log_info(cell);
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}
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}
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} FsmInfoPass;
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PRIVATE_NAMESPACE_END
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