mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
Although it is always possible to destroy and recreate the design to simulate a power-on reset, this has two drawbacks: * Black boxes are also destroyed and recreated, which causes them to reacquire their resources, which might be costly and/or erase important state. * Pointers into the design are invalidated and have to be acquired again, which is costly and might be very inconvenient if they are captured elsewhere (especially through the C API). |
||
---|---|---|
.. | ||
aiger | ||
blif | ||
btor | ||
cxxrtl | ||
edif | ||
firrtl | ||
intersynth | ||
json | ||
protobuf | ||
rtlil | ||
simplec | ||
smt2 | ||
smv | ||
spice | ||
table | ||
verilog |