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yosys/techlibs/intel_alm/common
Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
..
abc9_map.v
abc9_model.v
abc9_unmap.v
alm_map.v
alm_sim.v
arith_alm_map.v
bram_m10k.txt
bram_m20k.txt
bram_m20k_map.v
dff_map.v
dff_sim.v
dsp_map.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
dsp_sim.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
lutram_mlab.txt
megafunction_bb.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
mem_sim.v
quartus_rename.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00