mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
796 lines
25 KiB
C++
796 lines
25 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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*/
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#if !defined(__wasm)
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#include <filesystem>
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#endif
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#include "verilog_frontend.h"
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#include "verilog_lexer.h"
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#include "verilog_error.h"
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#include "verilog_location.h"
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#include "preproc.h"
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#include "kernel/yosys.h"
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#include "libs/sha1/sha1.h"
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#include <stdarg.h>
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#include <list>
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YOSYS_NAMESPACE_BEGIN
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using namespace VERILOG_FRONTEND;
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// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
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static std::vector<std::string> verilog_defaults;
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static std::list<std::vector<std::string>> verilog_defaults_stack;
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static void error_on_dpi_function(AST::AstNode *node)
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{
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if (node->type == AST::AST_DPI_FUNCTION)
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err_at_loc(node->location, "Found DPI function %s.\n", node->str);
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for (auto& child : node->children)
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error_on_dpi_function(child.get());
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}
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static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std::vector<std::unique_ptr<AST::AstNode>> &package_list)
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{
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// prime the parser's user type lookup table with the package qualified names
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// of typedefed names in the packages seen so far.
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for (const auto &pkg : package_list) {
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log_assert(pkg->type==AST::AST_PACKAGE);
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for (const auto &node: pkg->children) {
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if (node->type == AST::AST_TYPEDEF) {
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std::string s = pkg->str + "::" + node->str.substr(1);
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user_types[s] = node.get();
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}
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}
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}
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}
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" read_verilog [options] [filename]\n");
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log("\n");
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log("Load modules from a Verilog file to the current design. A large subset of\n");
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log("Verilog-2005 is supported.\n");
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log("\n");
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log(" -sv\n");
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log(" enable support for SystemVerilog features. (only a small subset\n");
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log(" of SystemVerilog is supported)\n");
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log("\n");
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log(" -formal\n");
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log(" enable support for SystemVerilog assertions and some Yosys extensions\n");
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log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
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log("\n");
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log(" -nosynthesis\n");
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log(" don't add implicit -D SYNTHESIS\n");
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log("\n");
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log(" -noassert\n");
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log(" ignore assert() statements\n");
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log("\n");
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log(" -noassume\n");
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log(" ignore assume() statements\n");
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log("\n");
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log(" -norestrict\n");
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log(" ignore restrict() statements\n");
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log("\n");
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log(" -assume-asserts\n");
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log(" treat all assert() statements like assume() statements\n");
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log("\n");
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log(" -assert-assumes\n");
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log(" treat all assume() statements like assert() statements\n");
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log("\n");
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log(" -nodisplay\n");
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log(" suppress output from display system tasks ($display et. al).\n");
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log(" This does not affect the output from a later 'sim' command.\n");
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log("\n");
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log(" -debug\n");
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log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
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log("\n");
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log(" -dump_ast1\n");
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log(" dump abstract syntax tree (before simplification)\n");
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log("\n");
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log(" -dump_ast2\n");
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log(" dump abstract syntax tree (after simplification)\n");
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log("\n");
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log(" -no_dump_ptr\n");
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log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
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log("\n");
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log(" -dump_vlog1\n");
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log(" dump ast as Verilog code (before simplification)\n");
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log("\n");
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log(" -dump_vlog2\n");
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log(" dump ast as Verilog code (after simplification)\n");
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log("\n");
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log(" -dump_rtlil\n");
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log(" dump generated RTLIL netlist\n");
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log("\n");
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log(" -yydebug\n");
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log(" enable parser debug output\n");
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log("\n");
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log(" -nolatches\n");
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log(" usually latches are synthesized into logic loops\n");
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log(" this option prohibits this and sets the output to 'x'\n");
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log(" in what would be the latches hold condition\n");
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log("\n");
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log(" this behavior can also be achieved by setting the\n");
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log(" 'nolatches' attribute on the respective module or\n");
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log(" always block.\n");
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log("\n");
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log(" -nomem2reg\n");
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log(" under certain conditions memories are converted to registers\n");
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log(" early during simplification to ensure correct handling of\n");
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log(" complex corner cases. this option disables this behavior.\n");
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log("\n");
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log(" this can also be achieved by setting the 'nomem2reg'\n");
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log(" attribute on the respective module or register.\n");
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log("\n");
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log(" This is potentially dangerous. Usually the front-end has good\n");
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log(" reasons for converting an array to a list of registers.\n");
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log(" Prohibiting this step will likely result in incorrect synthesis\n");
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log(" results.\n");
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log("\n");
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log(" -mem2reg\n");
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log(" always convert memories to registers. this can also be\n");
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log(" achieved by setting the 'mem2reg' attribute on the respective\n");
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log(" module or register.\n");
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log("\n");
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log(" -nomeminit\n");
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log(" do not infer $meminit cells and instead convert initialized\n");
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log(" memories to registers directly in the front-end.\n");
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log("\n");
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log(" -ppdump\n");
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log(" dump Verilog code after pre-processor\n");
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log("\n");
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log(" -nopp\n");
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log(" do not run the pre-processor\n");
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log("\n");
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log(" -nodpi\n");
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log(" disable DPI-C support\n");
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log("\n");
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log(" -noblackbox\n");
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log(" do not automatically add a (* blackbox *) attribute to an\n");
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log(" empty module.\n");
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log("\n");
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log(" -lib\n");
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log(" only create empty blackbox modules. This implies -DBLACKBOX.\n");
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log(" modules with the (* whitebox *) attribute will be preserved.\n");
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log(" (* lib_whitebox *) will be treated like (* whitebox *).\n");
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log("\n");
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log(" -nowb\n");
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log(" delete (* whitebox *) and (* lib_whitebox *) attributes from\n");
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log(" all modules.\n");
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log("\n");
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log(" -specify\n");
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log(" parse and import specify blocks\n");
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log("\n");
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log(" -noopt\n");
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log(" don't perform basic optimizations (such as const folding) in the\n");
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log(" high-level front-end.\n");
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log("\n");
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log(" -icells\n");
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log(" interpret cell types starting with '$' as internal cell types\n");
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log("\n");
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log(" -pwires\n");
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log(" add a wire for each module parameter\n");
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log("\n");
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log(" -nooverwrite\n");
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log(" ignore re-definitions of modules. (the default behavior is to\n");
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log(" create an error message if the existing module is not a black box\n");
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log(" module, and overwrite the existing module otherwise.)\n");
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log("\n");
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log(" -overwrite\n");
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log(" overwrite existing modules with the same name\n");
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log("\n");
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log(" -defer\n");
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log(" only read the abstract syntax tree and defer actual compilation\n");
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log(" to a later 'hierarchy' command. Useful in cases where the default\n");
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log(" parameters of modules yield invalid or not synthesizable code.\n");
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log("\n");
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log(" -noautowire\n");
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log(" make the default of `default_nettype be \"none\" instead of \"wire\".\n");
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log("\n");
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log(" -setattr <attribute_name>\n");
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log(" set the specified attribute (to the value 1) on all loaded modules\n");
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log("\n");
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log(" -Dname[=definition]\n");
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log(" define the preprocessor symbol 'name' and set its optional value\n");
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log(" 'definition'\n");
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log("\n");
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log(" -Idir\n");
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log(" add 'dir' to the directories which are used when searching include\n");
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log(" files\n");
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log("\n");
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log(" -relativeshare\n");
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log(" use paths relative to share directory for source locations\n");
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log(" where possible (experimental).\n");
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log("\n");
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log("The command 'verilog_defaults' can be used to register default options for\n");
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log("subsequent calls to 'read_verilog'.\n");
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log("\n");
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log("Note that the Verilog frontend does a pretty good job of processing valid\n");
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log("verilog input, but has not very good error reporting. It generally is\n");
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log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
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log("the syntax of the code, rather than to rely on read_verilog for that.\n");
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log("\n");
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log("Depending on if read_verilog is run in -formal mode, either the macro\n");
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log("SYNTHESIS or FORMAL is defined automatically, unless -nosynthesis is used.\n");
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log("In addition, read_verilog always defines the macro YOSYS.\n");
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log("\n");
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log("See the Yosys README file for a list of non-standard Verilog features\n");
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log("supported by the Yosys Verilog front-end.\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool flag_nodisplay = false;
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bool flag_dump_ast1 = false;
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bool flag_dump_ast2 = false;
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bool flag_no_dump_ptr = false;
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bool flag_dump_vlog1 = false;
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bool flag_dump_vlog2 = false;
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bool flag_dump_rtlil = false;
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bool flag_debug_lexer = false;
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bool flag_debug_parser = false;
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bool flag_nolatches = false;
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bool flag_nomeminit = false;
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bool flag_nomem2reg = false;
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bool flag_mem2reg = false;
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bool flag_ppdump = false;
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bool flag_nopp = false;
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bool flag_nodpi = false;
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bool flag_noopt = false;
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bool flag_icells = false;
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bool flag_pwires = false;
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bool flag_nooverwrite = false;
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bool flag_overwrite = false;
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bool flag_defer = false;
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bool flag_noblackbox = false;
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bool flag_nowb = false;
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bool flag_nosynthesis = false;
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bool flag_yydebug = false;
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bool flag_relative_share = false;
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define_map_t defines_map;
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std::list<std::string> include_dirs;
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std::list<std::string> attributes;
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ParseMode parse_mode = {};
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ParseState parse_state = {};
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parse_mode.sv = false;
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parse_mode.formal = false;
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parse_mode.noassert = false;
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parse_mode.noassume = false;
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parse_mode.norestrict = false;
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parse_mode.assume_asserts = false;
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parse_mode.assert_assumes = false;
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parse_mode.lib = false;
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parse_mode.specify = false;
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parse_state.default_nettype_wire = true;
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args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-sv") {
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parse_mode.sv = true;
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continue;
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}
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if (arg == "-formal") {
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parse_mode.formal = true;
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continue;
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}
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if (arg == "-nosynthesis") {
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flag_nosynthesis = true;
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continue;
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}
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if (arg == "-noassert") {
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parse_mode.noassert = true;
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continue;
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}
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if (arg == "-noassume") {
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parse_mode.noassume = true;
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continue;
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}
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if (arg == "-norestrict") {
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parse_mode.norestrict = true;
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continue;
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}
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if (arg == "-assume-asserts") {
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parse_mode.assume_asserts = true;
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continue;
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}
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if (arg == "-assert-assumes") {
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parse_mode.assert_assumes = true;
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continue;
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}
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if (arg == "-nodisplay") {
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flag_nodisplay = true;
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continue;
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}
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if (arg == "-debug") {
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flag_dump_ast1 = true;
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flag_dump_ast2 = true;
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flag_dump_vlog1 = true;
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flag_dump_vlog2 = true;
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flag_debug_lexer = true;
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flag_debug_parser = true;
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continue;
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}
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if (arg == "-dump_ast1") {
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flag_dump_ast1 = true;
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continue;
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}
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if (arg == "-dump_ast2") {
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flag_dump_ast2 = true;
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continue;
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}
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if (arg == "-no_dump_ptr") {
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flag_no_dump_ptr = true;
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continue;
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}
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if (arg == "-dump_vlog1") {
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flag_dump_vlog1 = true;
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continue;
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}
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if (arg == "-dump_vlog2") {
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flag_dump_vlog2 = true;
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continue;
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}
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if (arg == "-dump_rtlil") {
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flag_dump_rtlil = true;
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continue;
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}
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if (arg == "-yydebug") {
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flag_yydebug = true;
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flag_debug_lexer = true;
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flag_debug_parser = true;
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continue;
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}
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if (arg == "-nolatches") {
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flag_nolatches = true;
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continue;
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}
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if (arg == "-nomeminit") {
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flag_nomeminit = true;
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continue;
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}
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if (arg == "-nomem2reg") {
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flag_nomem2reg = true;
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continue;
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}
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if (arg == "-mem2reg") {
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flag_mem2reg = true;
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continue;
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}
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if (arg == "-ppdump") {
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flag_ppdump = true;
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continue;
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}
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if (arg == "-nopp") {
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flag_nopp = true;
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continue;
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}
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if (arg == "-nodpi") {
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flag_nodpi = true;
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continue;
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}
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if (arg == "-noblackbox") {
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flag_noblackbox = true;
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continue;
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}
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if (arg == "-lib") {
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parse_mode.lib = true;
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defines_map.add("BLACKBOX", "");
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continue;
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}
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if (arg == "-nowb") {
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flag_nowb = true;
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continue;
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}
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if (arg == "-specify") {
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parse_mode.specify = true;
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continue;
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}
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if (arg == "-noopt") {
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flag_noopt = true;
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continue;
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}
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if (arg == "-icells") {
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flag_icells = true;
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continue;
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}
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if (arg == "-pwires") {
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flag_pwires = true;
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continue;
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}
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if (arg == "-ignore_redef" || arg == "-nooverwrite") {
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flag_nooverwrite = true;
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flag_overwrite = false;
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continue;
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}
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if (arg == "-overwrite") {
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flag_nooverwrite = false;
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flag_overwrite = true;
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continue;
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}
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if (arg == "-defer") {
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flag_defer = true;
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continue;
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}
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if (arg == "-noautowire") {
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parse_state.default_nettype_wire = false;
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continue;
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}
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if (arg == "-setattr" && argidx+1 < args.size()) {
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attributes.push_back(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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if (arg == "-relativeshare") {
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flag_relative_share = true;
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log_experimental("read_verilog -relativeshare");
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continue;
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}
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if (arg == "-D" && argidx+1 < args.size()) {
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std::string name = args[++argidx], value;
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size_t equal = name.find('=');
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if (equal != std::string::npos) {
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value = name.substr(equal+1);
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name = name.substr(0, equal);
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}
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defines_map.add(name, value);
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continue;
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}
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if (arg.compare(0, 2, "-D") == 0) {
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size_t equal = arg.find('=', 2);
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std::string name = arg.substr(2, equal-2);
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std::string value;
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if (equal != std::string::npos)
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value = arg.substr(equal+1);
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defines_map.add(name, value);
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continue;
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}
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if (arg == "-I" && argidx+1 < args.size()) {
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include_dirs.push_back(args[++argidx]);
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continue;
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}
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if (arg.compare(0, 2, "-I") == 0) {
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include_dirs.push_back(arg.substr(2));
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (parse_mode.formal || !flag_nosynthesis)
|
|
defines_map.add(parse_mode.formal ? "FORMAL" : "SYNTHESIS", "1");
|
|
|
|
extra_args(f, filename, args, argidx);
|
|
|
|
log_header(design, "Executing Verilog-2005 frontend: %s\n", filename);
|
|
|
|
log("Parsing %s%s input from `%s' to AST representation.\n",
|
|
parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str());
|
|
|
|
log("verilog frontend filename %s\n", filename.c_str());
|
|
if (flag_relative_share) {
|
|
auto share_path = proc_share_dirname();
|
|
if (filename.substr(0, share_path.length()) == share_path)
|
|
filename = std::string("+/") + filename.substr(share_path.length());
|
|
log("new filename %s\n", filename.c_str());
|
|
}
|
|
AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv;
|
|
std::string code_after_preproc;
|
|
|
|
parse_state.lexin = f;
|
|
if (!flag_nopp) {
|
|
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode);
|
|
if (flag_ppdump)
|
|
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc);
|
|
parse_state.lexin = new std::istringstream(code_after_preproc);
|
|
}
|
|
|
|
auto filename_shared = std::make_shared<std::string>(filename);
|
|
auto top_loc = Location();
|
|
top_loc.begin.filename = filename_shared;
|
|
parse_state.current_ast = new AST::AstNode(top_loc, AST::AST_DESIGN);
|
|
VerilogLexer lexer(&parse_state, &parse_mode, filename_shared);
|
|
frontend_verilog_yy::parser parser(&lexer, &parse_state, &parse_mode);
|
|
lexer.set_debug(flag_debug_lexer);
|
|
parser.set_debug_level(flag_debug_parser ? 1 : 0);
|
|
|
|
// make package typedefs available to parser
|
|
add_package_types(parse_state.pkg_user_types, design->verilog_packages);
|
|
|
|
UserTypeMap global_types_map;
|
|
for (auto& def : design->verilog_globals) {
|
|
if (def->type == AST::AST_TYPEDEF) {
|
|
global_types_map[def->str] = def.get();
|
|
}
|
|
}
|
|
|
|
log_assert(parse_state.user_type_stack.empty());
|
|
// use previous global typedefs as bottom level of user type stack
|
|
parse_state.user_type_stack.push_back(std::move(global_types_map));
|
|
// add a new empty type map to allow overriding existing global definitions
|
|
parse_state.user_type_stack.push_back(UserTypeMap());
|
|
|
|
if (flag_yydebug) {
|
|
lexer.set_debug(true);
|
|
parser.set_debug_level(1);
|
|
}
|
|
parser.parse();
|
|
// frontend_verilog_yyset_lineno(1);
|
|
|
|
for (auto &child : parse_state.current_ast->children) {
|
|
if (child->type == AST::AST_MODULE)
|
|
for (auto &attr : attributes)
|
|
if (child->attributes.count(attr) == 0)
|
|
child->attributes[attr] = AST::AstNode::mkconst_int(top_loc, 1, false);
|
|
}
|
|
|
|
if (flag_nodpi)
|
|
error_on_dpi_function(parse_state.current_ast);
|
|
|
|
AST::process(design, parse_state.current_ast, flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
|
|
flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, parse_mode.lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, parse_state.default_nettype_wire);
|
|
|
|
|
|
if (!flag_nopp)
|
|
delete parse_state.lexin;
|
|
|
|
// only the previous and new global type maps remain
|
|
log_assert(parse_state.user_type_stack.size() == 2);
|
|
parse_state.user_type_stack.clear();
|
|
|
|
delete parse_state.current_ast;
|
|
parse_state.current_ast = NULL;
|
|
|
|
log("Successfully finished Verilog frontend.\n");
|
|
}
|
|
} VerilogFrontend;
|
|
|
|
struct VerilogDefaults : public Pass {
|
|
VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" verilog_defaults -add [options]\n");
|
|
log("\n");
|
|
log("Add the specified options to the list of default options to read_verilog.\n");
|
|
log("\n");
|
|
log("\n");
|
|
log(" verilog_defaults -clear\n");
|
|
log("\n");
|
|
log("Clear the list of Verilog default options.\n");
|
|
log("\n");
|
|
log("\n");
|
|
log(" verilog_defaults -push\n");
|
|
log(" verilog_defaults -pop\n");
|
|
log("\n");
|
|
log("Push or pop the list of default options to a stack. Note that -push does\n");
|
|
log("not imply -clear.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design*) override
|
|
{
|
|
if (args.size() < 2)
|
|
cmd_error(args, 1, "Missing argument.");
|
|
|
|
if (args[1] == "-add") {
|
|
verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end());
|
|
return;
|
|
}
|
|
|
|
if (args.size() != 2)
|
|
cmd_error(args, 2, "Extra argument.");
|
|
|
|
if (args[1] == "-clear") {
|
|
verilog_defaults.clear();
|
|
return;
|
|
}
|
|
|
|
if (args[1] == "-push") {
|
|
verilog_defaults_stack.push_back(verilog_defaults);
|
|
return;
|
|
}
|
|
|
|
if (args[1] == "-pop") {
|
|
if (verilog_defaults_stack.empty()) {
|
|
verilog_defaults.clear();
|
|
} else {
|
|
verilog_defaults.swap(verilog_defaults_stack.back());
|
|
verilog_defaults_stack.pop_back();
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
} VerilogDefaults;
|
|
|
|
struct VerilogDefines : public Pass {
|
|
VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" verilog_defines [options]\n");
|
|
log("\n");
|
|
log("Define and undefine verilog preprocessor macros.\n");
|
|
log("\n");
|
|
log(" -Dname[=definition]\n");
|
|
log(" define the preprocessor symbol 'name' and set its optional value\n");
|
|
log(" 'definition'\n");
|
|
log("\n");
|
|
log(" -Uname[=definition]\n");
|
|
log(" undefine the preprocessor symbol 'name'\n");
|
|
log("\n");
|
|
log(" -reset\n");
|
|
log(" clear list of defined preprocessor symbols\n");
|
|
log("\n");
|
|
log(" -list\n");
|
|
log(" list currently defined preprocessor symbols\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
std::string arg = args[argidx];
|
|
if (arg == "-D" && argidx+1 < args.size()) {
|
|
std::string name = args[++argidx], value;
|
|
size_t equal = name.find('=');
|
|
if (equal != std::string::npos) {
|
|
value = name.substr(equal+1);
|
|
name = name.substr(0, equal);
|
|
}
|
|
design->verilog_defines->add(name, value);
|
|
continue;
|
|
}
|
|
if (arg.compare(0, 2, "-D") == 0) {
|
|
size_t equal = arg.find('=', 2);
|
|
std::string name = arg.substr(2, equal-2);
|
|
std::string value;
|
|
if (equal != std::string::npos)
|
|
value = arg.substr(equal+1);
|
|
design->verilog_defines->add(name, value);
|
|
continue;
|
|
}
|
|
if (arg == "-U" && argidx+1 < args.size()) {
|
|
std::string name = args[++argidx];
|
|
design->verilog_defines->erase(name);
|
|
continue;
|
|
}
|
|
if (arg.compare(0, 2, "-U") == 0) {
|
|
std::string name = arg.substr(2);
|
|
design->verilog_defines->erase(name);
|
|
continue;
|
|
}
|
|
if (arg == "-reset") {
|
|
design->verilog_defines->clear();
|
|
continue;
|
|
}
|
|
if (arg == "-list") {
|
|
design->verilog_defines->log();
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (args.size() != argidx)
|
|
cmd_error(args, argidx, "Extra argument.");
|
|
}
|
|
} VerilogDefines;
|
|
|
|
#if !defined(__wasm)
|
|
|
|
static void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path)
|
|
{
|
|
std::ifstream flist(file_list_path);
|
|
if (!flist.is_open()) {
|
|
log_error("Verilog file list file does not exist");
|
|
exit(1);
|
|
}
|
|
|
|
std::filesystem::path file_list_parent_dir = std::filesystem::path(file_list_path).parent_path();
|
|
|
|
std::string v_file_name;
|
|
while (std::getline(flist, v_file_name)) {
|
|
if (v_file_name.empty()) {
|
|
continue;
|
|
}
|
|
|
|
std::filesystem::path verilog_file_path;
|
|
if (relative_to_file_list_path) {
|
|
verilog_file_path = file_list_parent_dir / v_file_name;
|
|
} else {
|
|
verilog_file_path = std::filesystem::current_path() / v_file_name;
|
|
}
|
|
|
|
bool is_sv = (verilog_file_path.extension() == ".sv");
|
|
|
|
std::vector<std::string> read_verilog_cmd = {"read_verilog", "-defer"};
|
|
if (is_sv) {
|
|
read_verilog_cmd.push_back("-sv");
|
|
}
|
|
read_verilog_cmd.push_back(verilog_file_path.string());
|
|
Pass::call(design, read_verilog_cmd);
|
|
}
|
|
|
|
flist.close();
|
|
}
|
|
|
|
struct VerilogFileList : public Pass {
|
|
VerilogFileList() : Pass("read_verilog_file_list", "parse a Verilog file list") {}
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" read_verilog_file_list [options]\n");
|
|
log("\n");
|
|
log("Parse a Verilog file list, and pass the list of Verilog files to read_verilog\n");
|
|
log("command\n");
|
|
log("\n");
|
|
log(" -F file_list_path\n");
|
|
log(" File list file contains list of Verilog files to be parsed, any path is\n");
|
|
log(" treated relative to the file list file\n");
|
|
log("\n");
|
|
log(" -f file_list_path\n");
|
|
log(" File list file contains list of Verilog files to be parsed, any path is\n");
|
|
log(" treated relative to current working directroy\n");
|
|
log("\n");
|
|
}
|
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
std::string arg = args[argidx];
|
|
if (arg == "-F" && argidx + 1 < args.size()) {
|
|
std::string file_list_path = args[++argidx];
|
|
parse_file_list(file_list_path, design, true);
|
|
continue;
|
|
}
|
|
if (arg == "-f" && argidx + 1 < args.size()) {
|
|
std::string file_list_path = args[++argidx];
|
|
parse_file_list(file_list_path, design, false);
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
|
|
extra_args(args, argidx, design, false);
|
|
}
|
|
} VerilogFilelist;
|
|
|
|
#endif
|
|
|
|
YOSYS_NAMESPACE_END
|