mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-01 03:44:05 +00:00
Code Activity
yosys/techlibs/common
History
Claire Xenia Wolf 92e705cb51 Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
..
.gitignore
abc9_map.v
abc9_model.v abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
abc9_unmap.v abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
adff2dff.v Fix syntax error in adff2dff.v 2021-02-24 01:07:34 +01:00
cellhelp.py
cells.lib
cmp2lcu.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
cmp2lut.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
pmux2mux.v
prep.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
simcells.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
simlib.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
synth.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
techmap.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00