| .. |
|
tests
|
Improved xilinx "bram1" test
|
2015-04-09 17:12:12 +02:00 |
|
.gitignore
|
Added support for initialized xilinx brams
|
2015-04-06 17:07:10 +02:00 |
|
arith_map.v
|
Fixed trailing whitespaces
|
2015-07-02 11:14:30 +02:00 |
|
brams.txt
|
Added read-enable to memory model
|
2015-09-25 12:23:11 +02:00 |
|
brams_bb.v
|
Added Xilinx bram black-box modules
|
2015-04-06 08:44:30 +02:00 |
|
brams_init.py
|
Squelch trailing whitespace, including meta-whitespace
|
2018-03-11 16:03:41 +01:00 |
|
brams_map.v
|
Added read-enable to memory model
|
2015-09-25 12:23:11 +02:00 |
|
cells_map.v
|
Improving vpr output support.
|
2018-04-18 16:55:12 -07:00 |
|
cells_sim.v
|
Add Xilinx RAM64X1D and RAM128X1D simulation models
|
2018-03-07 17:31:48 +01:00 |
|
cells_xtra.sh
|
Add inout ports to cells_xtra.v
|
2018-10-04 11:30:55 +02:00 |
|
cells_xtra.v
|
Add inout ports to cells_xtra.v
|
2018-10-04 11:30:55 +02:00 |
|
drams.txt
|
Added memory_bram "make_outreg" feature
|
2015-04-09 16:08:54 +02:00 |
|
drams_map.v
|
Xilinx DRAMS: RAM64X1D, RAM128X1D
|
2015-04-09 13:37:07 +02:00 |
|
lut2lut.v
|
Add techlibs/xilinx/lut2lut.v
|
2017-07-10 12:09:05 +02:00 |
|
Makefile.inc
|
Add Xilinx RAM64X1D and RAM128X1D simulation models
|
2018-03-07 17:31:48 +01:00 |
|
synth_xilinx.cc
|
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
|
2018-10-08 16:52:12 -07:00 |
