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Code Activity
yosys/backends
History
Miodrag Milanović 9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
..
aiger write_xaiger: create holes_sigmap before modifications 2020-01-11 17:25:32 -08:00
blif
btor Use cell name for btor bad state props when it is a public name 2019-11-14 11:57:38 +01:00
edif remove whitespace 2020-01-10 12:38:03 +01:00
firrtl Merge pull request #1258 from YosysHQ/eddie/cleanup 2019-08-10 09:52:14 +02:00
ilang
intersynth
json
protobuf Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
simplec
smt2 Bugfix in smtio vcd handling of $-identifiers 2019-10-23 00:04:34 +02:00
smv
spice
table
verilog write_verilog: add -extmem option, to write split memory init files. 2019-11-18 01:27:21 +00:00