mirror of
https://github.com/YosysHQ/yosys
synced 2026-06-14 04:45:40 +00:00
3 lines
71 B
Systemverilog
3 lines
71 B
Systemverilog
module sv_top(input logic a, output logic y);
|
|
assign y = a;
|
|
endmodule
|