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yosys
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5998c101a4
yosys
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techlibs
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Clifford Wolf
5998c101a4
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
..
cmos
Added spice testbench to techlibs/cmos
2013-09-14 13:29:11 +02:00
common
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
xilinx7
Added map, par and bitgen to xlinx7 example
2013-10-16 10:57:18 +02:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00