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yosys/techlibs/gowin
YRabbit 5821ca265a Gowin. BUGFIX. Restore MUXes.
I mistakenly listed MUXes as unplanned. This did not lead to
catastrophic consequences - all apicula and uLinux examples compile and
work, but the quality of synthesis was significantly reduced, which
affected the compilation time badly.

Restoring the MUXes will bring the compilation time back to normal.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-03-29 14:52:53 +10:00
..
arith_map.v gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
brams.txt gowin: Change BYTE ENABLE handling. 2024-01-27 17:19:49 +10:00
brams_map.v gowin: Fix SDP write enable port. 2024-01-30 17:06:59 +10:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v Update ALU MULT mode in gowin to match nextpnr 2024-12-23 11:12:48 +01:00
cells_xtra.py Gowin. BUGFIX. Restore MUXes. 2025-03-29 14:52:53 +10:00
cells_xtra_gw1n.v Gowin. BUGFIX. Restore MUXes. 2025-03-29 14:52:53 +10:00
cells_xtra_gw2a.v Gowin. BUGFIX. Restore MUXes. 2025-03-29 14:52:53 +10:00
cells_xtra_gw5a.v Gowin. BUGFIX. Restore MUXes. 2025-03-29 14:52:53 +10:00
lutrams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
synth_gowin.cc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00