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yosys/techlibs/intel_alm/common
History
Claire Xenia Wolf 92e705cb51 Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
..
abc9_map.v
abc9_model.v
abc9_unmap.v
alm_map.v
alm_sim.v intel_alm: Fix illegal carry chains 2021-05-15 22:37:06 +01:00
arith_alm_map.v intel_alm: Fix illegal carry chains 2021-05-15 22:37:06 +01:00
bram_m10k.txt
bram_m20k.txt
bram_m20k_map.v Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
dff_map.v
dff_sim.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
dsp_map.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
dsp_sim.v intel_alm: Add multiply signedness to cells 2020-08-26 22:50:16 +02:00
lutram_mlab.txt
megafunction_bb.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
mem_sim.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
misc_sim.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00
quartus_rename.v intel_alm: Add global buffer insertion 2021-05-15 22:37:06 +01:00