mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
83 lines
2.7 KiB
Text
83 lines
2.7 KiB
Text
# Generated by Yosys 0.40+7 (git sha1 4fd5b29f9, g++ 13.2.0 -Og -fPIC)
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autoidx 19
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attribute \cells_not_processed 1
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attribute \src "dff.v:1.1-16.10"
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module \gold
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attribute \src "dff.v:8.5-14.8"
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wire $0\q[0:0]
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attribute \init 1'0
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wire $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
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attribute \init 1'1
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wire $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
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attribute \init 1'0
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wire $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
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attribute \init 1'x
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wire $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
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wire $auto$rtlil.cc:2525:Eqx$10
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wire $auto$rtlil.cc:2582:Mux$12
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wire $auto$rtlil.cc:2582:Mux$16
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wire $auto$rtlil.cc:2582:Mux$18
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attribute \src "dff.v:2.16-2.19"
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wire input 1 \clk
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attribute \src "dff.v:4.16-4.17"
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wire input 3 \d
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attribute \keep 1
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attribute \src "dff.v:5.16-5.17"
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wire output 4 \q
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attribute \src "dff.v:3.16-3.21"
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wire input 2 \reset
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cell $mux $auto$clk2fflogic.cc:113:mux$11
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parameter \WIDTH 1
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connect \A $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
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connect \B $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
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connect \S $auto$rtlil.cc:2525:Eqx$10
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connect \Y $auto$rtlil.cc:2582:Mux$12
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end
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cell $mux $auto$clk2fflogic.cc:113:mux$15
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parameter \WIDTH 1
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connect \A $auto$rtlil.cc:2582:Mux$12
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connect \B 1'0
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connect \S $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
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connect \Y $auto$rtlil.cc:2582:Mux$16
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end
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cell $mux $auto$clk2fflogic.cc:113:mux$17
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parameter \WIDTH 1
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connect \A $auto$rtlil.cc:2582:Mux$16
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connect \B 1'0
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connect \S \reset
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connect \Y $auto$rtlil.cc:2582:Mux$18
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end
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cell $ff $auto$clk2fflogic.cc:70:sample_control$14
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parameter \WIDTH 1
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connect \D \reset
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connect \Q $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
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end
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cell $ff $auto$clk2fflogic.cc:82:sample_control_edge$8
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parameter \WIDTH 1
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connect \D \clk
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connect \Q $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
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end
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cell $eqx $auto$clk2fflogic.cc:83:sample_control_edge$9
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parameter \A_SIGNED 0
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parameter \A_WIDTH 2
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parameter \B_SIGNED 0
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parameter \B_WIDTH 2
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parameter \Y_WIDTH 1
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connect \A { $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 \clk }
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connect \B 2'01
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connect \Y $auto$rtlil.cc:2525:Eqx$10
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end
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attribute \clk2fflogic 1
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cell $ff $auto$clk2fflogic.cc:98:sample_data$4
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parameter \WIDTH 1
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connect \D \q
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connect \Q $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
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end
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cell $ff $auto$clk2fflogic.cc:98:sample_data$6
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parameter \WIDTH 1
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connect \D \d
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connect \Q $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
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end
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connect $0\q[0:0] \d
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connect \q $auto$rtlil.cc:2582:Mux$18
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end
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