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27 lines
483 B
Verilog
27 lines
483 B
Verilog
module bar(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire [1:0] inp;
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output reg [1:0] out;
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always @(inp)
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(* full_case, parallel_case *)
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case(inp)
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2'd0: out <= 2'd3;
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2'd1: out <= 2'd2;
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2'd2: out <= 2'd1;
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2'd3: out <= 2'd0;
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endcase
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endmodule
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module foo(clk, rst, inp, out);
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input wire clk;
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input wire rst;
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input wire [1:0] inp;
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output wire [1:0] out;
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bar bar_instance (clk, rst, inp, out);
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endmodule
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