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Code Activity
yosys/techlibs/common
History
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
..
.gitignore
abc9_map.v abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 2020-05-14 16:44:35 -07:00
abc9_model.v
abc9_unmap.v abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
adff2dff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cellhelp.py
cells.lib
cmp2lcu.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cmp2lut.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
dff2ff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
gate2lut.v
gen_fine_ffs.py simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Makefile.inc
mul2dsp.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
pmux2mux.v
prep.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
simcells.v simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
simlib.v Add new builtin FF types 2020-06-23 15:40:02 +02:00
synth.cc Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
techmap.v Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00