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https://github.com/YosysHQ/yosys
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41 lines
1.4 KiB
Text
41 lines
1.4 KiB
Text
read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 3 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 6 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-min 13 t:SB_LUT4
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select -assert-max 14 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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