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51 lines
1.5 KiB
Text
51 lines
1.5 KiB
Text
read_verilog -icells <<EOT
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module adlatch0(input E, R, D, output [2:0] Q);
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$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
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$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
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$_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
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endmodule
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module adlatch1(input E, R, D, output [2:0] Q);
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$_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
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$_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
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$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
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endmodule
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module top(input C, E, R, D, output [5:0] Q);
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adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0]));
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adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3]));
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endmodule
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EOT
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design -save orig
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flatten
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equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
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equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
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# Convert everything to ADLATCHs.
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design -load orig
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dfflegalize -cell $_DLATCH_PP0_ x
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select -assert-count 2 adlatch0/t:$_NOT_
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select -assert-count 8 adlatch1/t:$_NOT_
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select -assert-count 0 adlatch0/t:$_MUX_
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select -assert-count 0 adlatch1/t:$_MUX_
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select -assert-count 6 t:$_DLATCH_PP0_
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select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
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# Convert everything to DLATCHSRs.
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design -load orig
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dfflegalize -cell $_DLATCHSR_PPP_ x
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select -assert-count 2 adlatch0/t:$_NOT_
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select -assert-count 2 adlatch1/t:$_NOT_
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select -assert-count 0 adlatch0/t:$_MUX_
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select -assert-count 0 adlatch1/t:$_MUX_
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select -assert-count 6 t:$_DLATCHSR_PPP_
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select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
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