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55dc5a4e4f
* xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
17 lines
638 B
Verilog
17 lines
638 B
Verilog
(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
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module $__DFF_x__$abc9_flop (input C, D, (* init = 1'b0 *) input Q, output n1);
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parameter _TECHMAP_CELLTYPE_ = "";
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generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
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$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
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else if (_TECHMAP_CELLTYPE_ == "$__DFF_P__$abc9_flop")
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$_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
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else if (_TECHMAP_CELLTYPE_ != "")
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$error("Unrecognised _TECHMAP_CELLTYPE_");
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endgenerate
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endmodule
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module $__ABC9_SCC_BREAKER (input [WIDTH-1:0] I, output [WIDTH-1:0] O);
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parameter WIDTH = 0;
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assign O = I;
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endmodule
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